The ongoing reduction in size of electronic device elements poses problems in device performance which must be addressed using new materials and fabrication techniques. In the case of gate structures for high-performance CMOS devices, the equivalent oxide thickness of the gate dielectric has been reduced to about 1.2 nm. A typical CMOS gate structure is shown schematically in FIG. 1. Gate structure 10 is fabricated on the surface of substrate 1, which has source and drain regions 2, 3 formed therein. Gate structure 10 includes conducting element 11 (typically polysilicon; p+ doped and n+ doped in PFETs and NFETs respectively) overlying dielectric layer 12 If a conventional oxynitride gate dielectric is used, decreasing the thickness below about 1.2 nm (equivalent oxide thickness) causes the gate leakage current to become unacceptably high. In a structure such as shown in FIG. 1, the total gate electrical thickness may be viewed as having three components: the equivalent oxide thickness of the gate dielectric (about 1.2 nm), the quantum-mechanical effect of the substrate (about 0.4 nm), and the polysilicon depletion effect (about 0.3 to 0.4 nm). With present-day gate dielectric thicknesses, the polysilicon depletion effect accounts for a substantial component of the total gate electrical thickness. The polysilicon depletion effect occurs when the gate is turned on and a region devoid of charge forms at the polysilicon/dielectric interface (interface 12a in FIG. 1). The appearance of this depletion region reduces the capacitance of the gate and thus increases the electrical thickness. If the polysilicon depletion region could be eliminated, the electrical dielectric thickness would be reduced with no substantial increase in the leakage current. This would permit improved device performance without a further reduction in the thickness of the gate dielectric 12.
Linewidths are also being reduced to less than 65 nm. In the case of CMOS, this means that the lateral extent of gate structure 10 is now in the sub-65 nm range. If a gate structure about this size is designed with a gate dielectric equivalent thickness of about 1 nm, a conventional oxynitride gate dielectric can no longer be used due to unacceptably high leakage currents. It then becomes necessary to substitute high-k gate dielectric materials for the conventional gate oxide or oxynitride; this serves to lower the gate leakage current by 4 to 5 orders of magnitude.
However, the combination of polysilicon for the gate conductor 11 with a high-k material for the gate dielectric 12 presents further problems. As is understood by those skilled in the art, interactions between the materials can cause a shift in the threshold voltage Vt due to pinning of the Fermi level in the gate conductor. In particular, an increased Vt may prevent proper function in a PFET. Another problem affecting PFET performance is that of penetration of boron from the p+ type polysilicon into the high-k dielectric and possibly into the channel region of the device; this effect renders the device unusable.
Accordingly, in a PFET device (at least) it is desirable to eliminate the polysilicon from the gate structure (or at least remove the polysilicon from contact with the gate dielectric), as several benefits may be obtained. The elimination of the polysilicon depletion effect would decrease the effective electrical thickness of the gate dielectric. Interactions between the polysilicon and gate dielectric materials would be avoided, which in turn would avoid the problem of boron penetration. This would lead to faster devices which consume less power.
Recently there has been substantial interest in replacing polysilicon gate conductors with metal gate electrodes, so that the gate conductor 11 is a metal in both NFET and PFET devices. In order to provide appropriate threshold voltages in the two types of devices, two different metals are typically needed. In addition, the NFET and PFET require metals with different workfunctions. Generally an NFET device should have a workfunction in the range 4.1 to 4.3 eV; a PFET device should have a workfunction over 5.0 eV. Furthermore, the interface 12a between the metal and the gate dielectric should be stable during the high-temperature processing steps in the fabrication of the CMOS devices.
There are two possible integration approaches for metal gate conductors in CMOS; these are referred to as the “conventional processing” approach and the “replacement gate” approach. In the conventional processing approach, the metal is in contact with the gate dielectric during the high-temperature (above 1000° C.) activation annealing steps for the dopants in the source and drain regions. The metal must not interact with the dielectric material during the annealing steps. In the replacement gate approach, the CMOS structure is first formed with polysilicon gate electrodes; after all of the high-temperature processing steps, the polysilicon and gate dielectric are removed and a new dielectric is formed, followed by deposition of the metal gate conductor. With this approach the metal/dielectric interface need be stable only up to about 500° C.
It therefore is desirable that CMOS PFET and NFET devices be fabricated with gate structures that avoid the above-described problems of polysilicon depletion, leakage current, and boron penetration, and are also thermally stable when used in conjunction with either an oxynitride gate dielectric or a high-k gate dielectric. Such structures would allow for faster devices that consume less power, particularly when high-k gate dielectrics are used.